Silicon-on-insulator (SOI) device fabrication technologies use SOI wafers to fabricate a wide variety of different high-performance and low-power semiconductor devices and circuits. An SOI wafer typically has an electrically insulating buried oxide (BOX) layer between a top portion that includes a thin layer of silicon in which transistors and other active devices are formed and a bottom bulk silicon wafer. In some examples, all of the active device and integrated circuit processing is performed on the SOI wafer. As a result of the electrical isolation between the thin silicon layer and the bulk silicon wafer, these active devices tend to operate with higher performance and lower power than comparable devices that are fabricated directly on bulk silicon wafers. In other examples, a layer transfer process is used to transfer a top active device portion of an SOI wafer to a handle wafer. In this process, the top portion of the SOI wafer is bonded to the handle wafer, and the bulk substrate and BOX layer of the SOI wafer are removed. In some examples, the handle wafer includes one or more trap rich layers between the active device layer and the bulk substrate of the handle wafer to inhibit parasitic surface conduction and enhance the RF performance of one or more devices on the handle wafer as described in, e.g., U.S. Pat. No. 8,466,036.
Although SOI wafer based device fabrication technologies offer many benefits, the high cost of SOI wafers, as compared to bulk semiconductor wafers, limits the use of these fabrication methods to only a small sub-set of the possible semiconductor device markets.